There is an ever-present desire in the semiconductor fabrication industry to achieve individual devices with smaller physical dimensions. Reducing the dimensions of devices is referred to as scaling. Scaling is desirable in order to increase the number of individual devices that can be placed on a given area of semiconductor material and the process yield and to reduce the unit cost and the power consumption of individual devices.
However, scaling often creates some drawbacks. In particular, it can be difficult to form contacts on silicide regions of the transistors, as a very small “footprint” of area is available for placement of the contact. This often imposes a height requirement on the contacts, in order to achieve the appropriate contact dimensions at the base where it contacts the silicide regions. Therefore, it is desirable to have an improved structure and method for use in the fabrication of field effect transistors.